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NXP Semiconductors /LPC18xx /I2S0 /RXBITRATE

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Interpret as RXBITRATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RX_BITRATE0RESERVED

Description

I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.

Fields

RX_BITRATE

I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data